MCM69P618C

1

MOTOROLA FAST SRAM

64K x 18 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM69P618C is a 1M–bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC

™, 486, i960™, and Pentium™ microprocessors. It is organized as 64K

words of 18 bits each. This device integrates input registers, an output register,

a 2–bit address counter, and high speed SRAM onto a single monolithic circuit

for reduced parts count in cache data RAM applications. Synchronous design

allows precise cycle control with the use of an external clock (K). BiCMOS cir-

cuitry reduces the overall power consumption of the integrated functions for

greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69P618C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and syn-

chronous write enable SW are provided to allow writes to either individual bytes

or to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa

and SBb controls DQb. Individual bytes are written if the selected byte writes SBx

are asserted with SW. Both bytes are written if either SGW is asserted or if both

SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

The MCM69P618C operates from a single 3.3 V power supply and all inputs

and outputs are LVTTL compatible and 5 V tolerant.

• MCM69P618C–4 = 4 ns Access / 7.5 ns Cycle

MCM69P618C–4.5 = 4.5 ns Access / 8 ns Cycle

MCM69P618C–5 = 5 ns Access / 10 ns Cycle

MCM69P618C–6 = 6 ns Access / 12 ns Cycle

MCM69P618C–7 = 7 ns Access / 13.3 ns Cycle

• Single 3.3 V + 10%, – 5% Power Supply

• ADSP, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• Single–Cycle Deselect Timing

• 5 V Tolerant on all Pins (Inputs and I/Os)

• 100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

Order this document

by MCM69P618C/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69P618C

TQ PACKAGE

TQFP

CASE 983A–01

REV 2

2/16/98