数据搜索系统,热门电子元器件搜索 |
|
SL74HC112N 数据表(PDF) 1 Page - System Logic Semiconductor |
|
SL74HC112N 数据表(HTML) 1 Page - System Logic Semiconductor |
1 / 6 page SL74HC112 System Logic Semiconductor SLS Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The SL74HC112 is identical in pinout to the LS/ALS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC112N Plastic SL74HC112D SOIC TA = -55 ° to 125° C for all packages FUNCTION TABLE Inputs Outputs Set Reset Clock J K Q Q L H X X X H L H L X X X L H L L X X X L * L * H H L L No Change H H L H L H H H H L H L H H H H Toggle H H L X X No Change H H H X X No Change H H X X No Change * Both output will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously X = Don’t Care LOGIC DIAGRAM PIN 16=VCC PIN 8 = GND PIN ASSIGNMENT |
类似零件编号 - SL74HC112N |
|
类似说明 - SL74HC112N |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |