MCM69Q618

7

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

3 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level

1.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load

Figure 1 Unless Otherwise Noted

. . . . . . . . . . . . . . . . . .

READ/WRITE CYCLE TIMING

P

Sb l

MCM69Q618–6

MCM69Q618–8

MCM69Q618–10

Ui

N

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Cycle Time

tKHKH

12

—

15

—

20

—

ns

1

Clock Access Time

tKHQV

—

6

—

8

—

10

ns

2

Clock Low Pulse Width

tKLKH

4

—

6

—

8

—

ns

Clock High Pulse Width

tKHKL

4

—

6

—

8

—

ns

Clock High to Data Output Invalid

tKHQX

0

—

0

—

0

—

ns

Clock High to Data Output High–Z

tKHQZ

—

5

—

6

—

7

ns

3

Output Enable to Output Valid

tGLQV

—

6

—

8

—

10

ns

Output Enable to Output Active

tGLQX

0

—

0

—

0

—

ns

3

Output Disable to Output High–Z

tGHQZ

—

5

—

6

—

7

ns

3

Setup Times:

A0 – A15

W

PT

E1, E2

D0 – D17

tAVKH

tWVKH

tPTVKH

tEVKH

tDVKH

2.5

—

3

—

3

—

ns

4

Hold Times:

A0 – A15

W

PT

E1, E2

D0 – D17

tKHAX

tKHWX

tKHPTX

tKHEX

tKHDX

0.5

—

2

—

2

—

ns

4

NOTES:

1. All read and write cycles are referenced from K.

2. Valid data from Clock High will be the data stored at the address or the last valid read cycle.

3. This parameter is sampled and not 100% tested.

4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for

ALL rising

edges of clock (K) while the device is selected.

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

Figure 1. AC Test Load