MCM69P735

6

MOTOROLA FAST SRAM

Rating

Symbol

Value

Unit

Power Supply Voltage

VDD

VSS – 0.5 to + 4.6

V

I/O Supply Voltage (See Note 2)

VDDQ

VSS – 0.5 to VDD

V

Input Voltage Relative to VSS for Any

Pin Except VDD (See Note 2)

Vin, Vout

VSS – 0.5 to

VDD + 0.5

V

Input Voltage (Three–State I/O)

(See Note 2)

VIT

VSS – 0.5 to

VDDQ + 0.5

V

Output Current (per I/O)

Iout

± 20

mA

Package Power Dissipation (See Note 3)

PD

1.6

W

Temperature Under Bias

Tbias

– 10 to 85

°C

Storage Temperature

Tstg

– 55 to 125

°C

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended

periods of time could affect device reliability.

2. This is a steady–state DC parameter that is in effect after the power supply has

achieved its nominal operating level. Power sequencing can not be controlled and

is not allowed.

3. Power dissipation capability is dependent upon package characteristics and use

environment. See Package Thermal Characteristics.

PACKAGE THERMAL CHARACTERISTICS — PBGA

Rating

Symbol

Max

Unit

Notes

Junction to Ambient (@ 200 lfm)

Single Layer Board

Four Layer Board

R

θJA

41

19

°C/W

1, 2

Junction to Board (Bottom)

R

θJB

11

°C/W

3

Junction to Case (Top)

R

θJC

9

°C/W

4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.