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MCM69F536CTQ12R 数据表(PDF) 4 Page - Motorola, Inc |
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MCM69F536CTQ12R 数据表(HTML) 4 Page - Motorola, Inc |
4 / 12 page MCM69F536C 4 MOTOROLA FAST SRAM PIN DESCRIPTIONS Pin Locations Symbol Type Description 85 ADSC Input Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle. 84 ADSP Input Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). 86 G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 89 K Input Clock: This signal registers the address, data in, and all control signals except G and LBO. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst count (68K/PowerPC). High — interleaved burst count (486/i960/Pentium). 32, 33, 34, 35, 44, 45, 46, 47, 48, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 VDD Supply Power Supply: 3.3 V + 10%, – 5%. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 64 NC Input No Connection: There is no connection to the chip. For compatibility reasons, it is recommended that this pin be tied low for system designs that do not have a sleep mode associated with the cache/memory controller. Other vendors’ RAMs may have implemented this Sleep Mode (ZZ) feature. 14, 16, 38, 39, 42, 43, 49, 50, 66 NC — No Connection: There is no connection to the chip. |
类似零件编号 - MCM69F536CTQ12R |
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类似说明 - MCM69F536CTQ12R |
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