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LTC3833 数据表(PDF) 32 Page - Linear Technology |
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LTC3833 数据表(HTML) 32 Page - Linear Technology |
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32 / 50 page  LTC3839 32 3839fa APPLICATIONS INFORMATION response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly 2nd order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The external series RITH-CITH1 filter at the ITH pin sets the dominant pole-zero loop compensation. The values can be adjusted to optimize transient response once the final PCB layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected first because their various types and values determine the loop feedback factor gain and phase. An additional small capacitor, CITH2, can be placed from the ITH pin to SGND to attenuate high frequency noise. Note this CITH2 contributes an additional pole in the loop gain therefore can affect system stability if too large. It should be chosen so that the added pole is higher than the loop bandwidth by a significant margin. The regulator loop response can also be checked by looking at the load transient response. An output current pulse of 20% to 100% of full-load current having a rise time of 1μs to 10μs will produce VOUT and ITH voltage transient-response waveforms that can give a sense of the overall loop stability without breaking the feedback loop. For a detailed explanation of OPTI-LOOP compensation, refer to Application Note 76. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT.∆ILOAD also begins to charge or discharge COUT, generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Connecting a resistive load in series with a power MOSFET, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condi- tion. The initial output voltage step resulting from the step change in load current may not be within the bandwidth of the feedback loop, so it cannot be used to determine phase margin. The output voltage settling behavior is more related to the stability of the closed-loop system. However, it is better to look at the filtered and compensated feedback loop response at the ITH pin. The gain of the loop increases with the RITH and the band- width of the loop increases with decreasing CITH1. If RITH is increased by the same factor that CITH1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor, CFF, can be added to improve the high frequency response, as shown in Figure 1. Capacitor CFF provides phase lead by creating a high frequency zero with RFB2 which improves the phase margin. A more severe transient can be caused by switching in loads with large supply bypass capacitors. The discharged bypass capacitors of the load are effectively put in parallel with the converter’s COUT, causing a rapid drop in VOUT. No regulator can deliver current quick enough to prevent this sudden step change in output voltage, if the switch connecting the COUT to the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. Hot Swap™ controllers are designed specifically for this purpose and usually incorporate current limiting, short-circuit protection and soft starting. Load-Release Transient Detection As the output voltage requirement of step-down switching regulators becomes lower, VIN to VOUT step-down ratio increases, and load transients become faster, a major challenge is to limit the overshoot in VOUT during a fast load current drop, or “load-release” transient. Inductor current slew rate diL/dt = VL/L is proportional to voltage across the inductor VL = VSW – VOUT. When the top MOSFET is turned on, VL = VIN – VOUT, inductor current ramps up. When bottom MOSFET turns on, VL = VSW – VOUT = –VOUT, inductor current ramps down. At very low VOUT, the low differential voltage, VL, across the inductor during the ramp down makes the slew rate of the inductor current much slower than needed to follow the load current change. The excess inductor current charges up the output capacitor, which causes overshoot at VOUT. |
类似零件编号 - LTC3833 |
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类似说明 - LTC3833 |
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