MCM67Q709A

3

MOTOROLA FAST SRAM

TRUTH TABLE

E

(tn)

W

(tn)

G

Mode

D0 – D8

(tn)

Q0 – Q8

(tn + 1)

VCC

Current

L

L

L

Write and

Pass–Through

Valid

D0 – D8 (tn)

ICC

H

Write

Valid

High–Z

ICC

H

L

L

Pass–Through

Valid

D0 – D8 (tn)

ICC

H

L

H

Pass–Through

Don’t Care

High–Z

ICC

X

H

L

Read

Don’t Care

Qout (tn)

ICC

X

H

H

Read

Don’t Care

High–Z

ICC

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC

– 0.5 to + 7.0

V

Voltage Relative to VSS for Any Pin

Except VCC

Vin, Vout

– 0.5 to VCC + 0.5

V

Output Current

Iout

± 30

mA

Power Dissipation

PD

1.5

W

Temperature Under Bias

Tbias

– 10 to + 85

°C

Operating Temperature

TA

0 to + 70

°C

Storage Temperature — Plastic

Tstg

– 55 to + 125

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS

Parameter

Symbol

Min

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.75

5.25

V

Input High Voltage

VIH

2.2

VCC + 0.3**

V

Input Low Voltage

VIL

– 0.5*

0.8

V

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Ilkg(I)

—

± 1.0

µA

Output Leakage Current (E = VIH, Vout = 0 to VCC)

Ilkg(O)

—

± 1.0

µA

AC Supply Current (Iout = 0 mA) (VCC = max, f = fmax)

MCM67Q709A–10 ns

ICCA

—

230

mA

Output Low Voltage (IOL = + 8.0 mA)

VOL

—

0.4

V

Output High Voltage (IOH = – 4.0 mA)

VOH

2.4

3.3

V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

Parameter

Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance

Cin

6

pF

Output Capacitance

Cout

8

pF

This is a synchronous device. All synchro-

nous inputs must meet specified setup and

hold times with stable logic levels for

ALL rising

edges of clock (K) while the device is selected.

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to these high–impedance

circuits.