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MCM67J518FN7 数据表(PDF) 5 Page - Motorola, Inc |
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MCM67J518FN7 数据表(HTML) 5 Page - Motorola, Inc |
5 / 12 page MCM67J518 5 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level 1.5 V . . . . . . . . . . . . . . . Input Pulse Levels 0 to 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Timing Reference Level 1.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Output Load See Figure 1A Unless Otherwise Noted . . . . . . . . . . . . READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4) MCM67J518–6 MCM67J518–7 MCM67J518–9 Parameter Symbol Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 10 — 12.5 — 15 — ns Clock Access Time tKHQV — 6 — 7 — 9 ns 5 Output Enable to Output Valid tGLQV — 5 — 5 — 6 ns Clock High to Output Active tKHQX1 2 — 2 — 2 — ns Clock High to Output Change tKHQX2 2 — 2 — 2 — ns Output Enable to Output Active tGLQX 0 — 0 — 0 — ns Output Disable to Q High–Z tGHQZ — 6 — 6 — 6 ns 6 Clock High to Q High–Z tKHQZ 2 6 2 6 2 6 ns Clock High Pulse Width tKHKL 4 — 5 — 5 — ns Clock Low Pulse Width tKLKH 4 — 5 — 5 — ns Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH 2.5 — 2.5 — 2.5 — ns 7 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX 0.5 — 0.5 — 0.5 — ns 7 NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible i486 amd Pentium external bus cycles. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled. AC TEST LOADS Figure 1A Figure 1B 5 pF + 5 V OUTPUT 480 Ω 255 Ω OUTPUT Z0 = 50 Ω RL = 50 Ω VL = 1.5 V |
类似零件编号 - MCM67J518FN7 |
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类似说明 - MCM67J518FN7 |
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