DRV8834RGER Datasheet(数据表) 16 Page - Texas Instruments
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DRV8834RGER Datasheet(HTML) 16 Page - Texas Instruments
SLVSB19A – FEBRUARY 2012 – REVISED MARCH 2012
When exiting sleep mode, the nFAULT pin will be briefly driven active low as the internal power supplies turn on.
nFAULT will return to inactive high once the internal power supplies (including charge pump) have stabilized.
This process takes some time (up to 1 ms), before the motor driver becomes fully operational.
The DRV8834 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time (t
), all FETs in the H-bridge will be disabled
and the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (approximately
1.2 ms) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle
repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Please
note that only the H-bridge in which the OCP is detected will be disabled while the other bridge will function
Overcurrent conditions are detected independently on both high and low side devices; i.e., a short to ground,
supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection
does not use the current sense circuitry used for PWM current control, so functions even without presence of the
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume and nFAULT
will become inactive.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold. The nFAULT pin is driven low during an undervoltage condition, and also at power-up or sleep mode,
until the internal power supplies have stabilized.
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