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MCM67B618AFN9 数据表(PDF) 1 Page - Motorola, Inc |
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MCM67B618AFN9 数据表(HTML) 1 Page - Motorola, Inc |
1 / 12 page MCM67B618A 1 MOTOROLA FAST SRAM 64K x 18 Bit BurstRAM ™ Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67B618A is a 1,179,648 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 ™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for re- duced parts count implementation of cache data RAM applications. Synchro- nous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated func- tions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge– triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM67B618A (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more de- tailed information on burst controls. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased flexibility for incoming signals. Dual write enables (LW and UW) are provided to allow individually write- able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information. • Single 5 V ± 5% Power Supply • Fast Access Times: 9/10/12 ns Max • Byte Writeable via Dual Write Enables • Internal Input Registers (Address, Data, Control) • Internally Self–Timed Write Cycle • ADSP, ADSC, and ADV Burst Control Pins • Asynchronous Output Enable Controlled Three–State Outputs • Common Data Inputs and Data Outputs • 3.3 V I/O Compatible • High Board Density 52–Lead PLCC Package BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp. 10 9 8 DQ9 VCC DQ8 12 11 15 14 13 17 16 20 19 18 37 38 34 35 36 42 43 39 40 41 45 46 44 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 54 32 1 52 51 50 49 48 47 DQ6 DQ7 VSS DQ4 DQ5 DQ2 DQ3 VSS VCC DQ0 DQ1 VCC VSS VSS VCC DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 All power supply and ground pins must be connected for proper operation of the device. PIN NAMES A0 – A15 Address Inputs . . . . . . . . . . . . . . . . K Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADV Burst Address Advance . . . . . . . . . . . . LW Lower Byte Write Enable . . . . . . . . . . . . UW Upper Byte Write Enable . . . . . . . . . . . . ADSC Controller Address Status . . . . . . . . . ADSP Processor Address Status . . . . . . . . . E Chip Enable . . . . . . . . . . . . . . . . . . . . . . . . . G Output Enable . . . . . . . . . . . . . . . . . . . . . . DQ0 – DQ17 Data Input/Output . . . . . . . . . . VCC + 5 V Power Supply . . . . . . . . . . . . . . . . VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . NC No Connection . . . . . . . . . . . . . . . . . . . . . PIN ASSIGNMENTS Order this document by MCM67B618A/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM67B618A FN PACKAGE PLASTIC CASE 778–02 REV 2 11/5/96 © Motorola, Inc. 1996 |
类似零件编号 - MCM67B618AFN9 |
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类似说明 - MCM67B618AFN9 |
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