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ADP7102ACPZ-9.0-R7 数据表(PDF) 4 Page - Analog Devices |
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ADP7102ACPZ-9.0-R7 数据表(HTML) 4 Page - Analog Devices |
4 / 28 page ADP7102 Data Sheet Rev. A | Page 4 of 28 Parameter Symbol Conditions Min Typ Max Unit PROGRAMMABLE EN/UVLO UVLO Threshold rising UVLORISE 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 1.18 1.23 1.28 V UVLO Threshold falling UVLOFALL 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in series with enable pin 1.13 V UVLO Hysteresis Current UVLOHYS VEN > 1.25 V, TJ = −40°C to +125°C 7.5 9.8 12 µA Enable Pulldown Current IEN-IN EN = VIN 500 nA INPUT VOLTAGE Start Threshold VSTART TJ = −40°C to +125°C 3.2 V Shutdown Threshold VSHUTDOWN TJ = −40°C to +125°C 2.45 V Hysteresis 250 mV OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 15 µV rms 10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V 15 µV rms 10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 15 µV rms 10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V 15 µV rms 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V, adjustable mode 18 µV rms 10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V, adjustable mode 30 µV rms 10 Hz to 100 kHz, VIN = 18 V, VOUT = 15 V, adjustable mode 65 µV rms POWER SUPPLY REJECTION RATIO PSRR 100 kHz, VIN = 4.3 V, VOUT = 3.3 V 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V 50 dB 10 kHz, VIN = 4.3 V, VOUT = 3.3 V 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V 60 dB 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 60 dB 100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 60 dB 10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 80 dB 10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 80 dB 1 Based on an end-point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 3.0 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Conditions Min Typ Max Unit Minimum Input and Output Capacitance1 CMIN TA = −40°C to +125°C 0.7 µF Capacitor ESR RESR TA = −40°C to +125°C 0.001 0.2 Ω 1 The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO. |
类似零件编号 - ADP7102ACPZ-9.0-R7 |
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类似说明 - ADP7102ACPZ-9.0-R7 |
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