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AD5685RARUZ 数据表(PDF) 6 Page - Analog Devices

部件名 AD5685RARUZ
功能描述  Quad, 16-/14-/12-Bit nanoDAC
Download  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5685RARUZ 数据表(HTML) 6 Page - Analog Devices

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AD5686R/AD5685R/AD5684R
Data Sheet
Rev. 0 | Page 6 of 32
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
1.8 V ≤ VLOGIC <
2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol
Min
Max
Min
Max
Unit
SCLK Cycle Time
t1
33
20
ns
SCLK High Time
t2
16
10
ns
SCLK Low Time
t3
16
10
ns
SYNC to SCLK Falling Edge Setup Time
t4
15
10
ns
Data Setup Time
t5
5
5
ns
Data Hold Time
t6
5
5
ns
SCLK Falling Edge to SYNC Rising Edge
t7
15
10
ns
Minimum SYNC High Time (Single, Combined or All Channel Update)
t8
20
20
ns
SYNC Falling Edge to SCLK Fall Ignore
t9
16
10
ns
LDAC Pulse Width Low
t10
25
15
ns
SCLK Falling Edge to LDAC Rising Edge
t11
30
20
ns
SCLK Falling Edge to LDAC Falling Edge
t12
20
20
ns
RESET Minimum Pulse Width Low
t13
30
30
ns
RESET Pulse Activation Time
t14
30
30
ns
Power-Up Time2
4.5
4.5
µs
1
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2
Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
Figure 2. Serial Write Operation
t4
t3
SCLK
SYNC
SDIN
t1
t2
t5
t6
t7
t8
DB23
t9
t10
t11
LDAC1
LDAC2
t12
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
RESET
t13
t14
VOUT
DB0


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