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MCM6706CR Datasheet(数据表) 3 Page - Motorola, Inc

部件型号  MCM6706CR
说明  32K x 8 Bit Static Random Access Memory
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制造商  MOTOROLA [Motorola, Inc]
网页  http://www.freescale.com
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MCM6706CR Datasheet(HTML) 3 Page - Motorola, Inc

   
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MCM6706CR
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Max
Unit
Address Input Capacitance
Cin
5
pF
Control Pin Input Capacitance (E, G, W)
Cin
6
pF
I/O Capacitance
Cout
6
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
2 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . .
Output Load
See Figure 1a
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE (See Notes 1 and 2)
MCM6706CR–5
MCM6706CR–5.5
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
5
5.5
ns
3
Address Access Time
tAVQV
5
5.5
ns
Chip Enable Access Time
tELQV
5
5.5
ns
Output Enable Access Time
tGLQV
4
4
ns
Output Hold from Address Change
tAXQX
2.0
2.0
ns
Chip Enable Low to Output Active
tELQX
3
3
ns
4 ,5, 6
Chip Enable High to Output High–Z
tEHQZ
3
3
ns
4, 5, 6
Output Enable Low to Output Active
tGLQX
0
0
ns
4, 5, 6
Output Enable High to Output High–Z
tGHQZ
3
3
ns
4, 5, 6
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V
(a)
(b)
5 pF
+5 V
OUTPUT
255
480
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
TIMING LIMITS
Figure 1. AC Test Loads




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