Atmel AT88SA100S [DATASHEET]

4

8558F

−CRYPTO−9/11

1.4

SHA-256 Computation

This chip performs only one cryptographic calculation – a keyed digest of an input challenge using the SHA-256 algorithm,

documented here:

http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf

1.4.1

SHA Computation Example

In order to ensure that there is no ambiguity, the following example vector is provided in addition to the sample vectors in the

NIST document. In this example, all values are listed in hex. For all but the key, bytes are listed in the order that they appear

on the bus – first on the left. Key is listed in the same order, so the 01 at the left of the key string is the first byte passed to

SHA-256.

SHA Computation Example

Key

01030507090B0D0F11131517191B1D1F21232527292B2D2F31333537393B3D3F

Challenge

020406080A0C0E10121416181A1C1E20222426282A2C2E30323436383A3C3E40

Opcode

08

Mode

40 (include serial number in message)

Param2

0000

Fuse MfrID

77

Fuse S/N

8899AABB

ROM MfrID

CCDD

ROM SN

EEFF

The 88-bytes over which the digest is calculated are:

0103…3D3F0204…3E4001400000…EEFF

Digest:

7D38245733717A488575B9F794F7BCAFE033A3848D39430DA25141FDEBEAA1C2

A read command executed on Address 0 of the ROM (ROM MfrID, ROM SN) would return CC DD EE FF, with CC being the

first byte on the bus and FF being the last.

Throughout this document, the complete message processed by the SA100S chip is documented. According to the above

specification, this always includes a single bit of ‘1’ pad after the message, followed by a 64-bit value representing the total

number of bits being hashed (less pad and length). If the length is less than 447 (512-64-1) then the necessary number of ‘0’

bits are included between the ‘1’ pad and ‘length’ to stretch the last message block out to 512-bits.

When using standard libraries to calculate the SHA-256 digest, these pad and length bits should probably not be passed to the

library as most standard software implementations of the algorithm add them in automatically.

1.5

Security Features

The AT88SA100S incorporates a number of physical security features designed to protect the key from unauthorized release.

These include an active shield over the entire surface of the internal memory encryption, internal clock generation, glitch

protection, voltage tamper detection and other physical design features.

Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two signals.