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AT87LV51-12AC 数据表(PDF) 6 Page - ATMEL Corporation

部件名 AT87LV51-12AC
功能描述  8-bit Microcontroller with 4K Bytes QuickFlash짰
Download  16 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT87LV51-12AC 数据表(HTML) 6 Page - ATMEL Corporation

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AT87LV51
6
Status of External Pins during Idle and Power-down Modes
Program Memory Lock Bits
The AT87LV51 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the
additional features listed in the table below:
Lock Bit Protection Modes
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
essary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
Programming the QuickFlash
The AT87LV51 is shipped with the on-chip QuickFlash
memory array ready to be programmed. The programming
interface needs a high-voltage (12-volt) program enable
signal and is compatible with conventional third-party
QuickFlash or EPROM programmers.
The AT87LV52 code memory array is programmed byte-
by-byte.
Programming Algorithm: Before programming the
AT87LV51, the address, data and control signals should be
set up according to the QuickFlash Programming Modes
table and Figure 3 and F igure 4. T o pr ogr a m the
AT87LV51, the following sequence should be followed:
1.
Input the desired memory location on the address
lines.
2.
Input the appropriate data byte on the data lines.
3.
Activate the correct combination of control signals.
4.
Raise EA/V
PP to 12V.
5.
Pulse ALE/PROG once to program a byte in the
QuickFlash array or the lock bits. The byte-write
cycle is self-timed and typically takes no more than
1.5 ms. Repeat steps 1 through 5, changing the
address and data for the entire array or until the end
of the object file is reached.
Data Polling: The AT87LV51 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P0.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H and 031H, except that P3.6 and P3.7 need
to be pulled to a logic low. The values returned are:
(030H) = 1EH indicates manufactured by Atmel
(031H) = 87H indicates 87F family
(032H) = 03H indicates 87LV51
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No program lock features.
2
P
U
U
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on
reset, and further
programming of the
QuickFlash is disabled.
3
P
P
U
Same as mode 2, also verify
is disabled.
4
P
P
P
Same as mode 3, also
external execution is
disabled.


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