COMMERCIALTEMPERATURERANGE

8

IDT74FCT388915T

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)

CMMU

CM MU

CPU

CM MU

CMMU

CM MU

CMMU

CM MU

CPU

CM MU

CMMU

CM MU

PLL

2f

PLL

2f

CPU

CARD

CPU

CARD

CLOCK

@f

SYSTEM

CLO CK

SO UR CE

FCT388915T

FCT388915T

DISTRIBUTE

CLO CK @ f

CLOCK @ 2f

at point of use

MEMORY

CO NTROL

PLL

2f

MEMORY

CAR DS

CLOCK @ 2f

at point of use

FCT388915T

Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication

and Low Board-to-Board skew

FCT388915T SYSTEM LEVEL TESTING

FUNCTIONALITY

When the PLL_EN pin is LOW, the PLL is bypassed and the FCT388915T

is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q

output is inverted from the selected SYNC input, and the Q outputs are divide-

by-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide-

by-4(negativeedgetriggered). WithFREQ_SELLOWthe2Qoutputisdivide-

by-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8.

These relationships can be seen in the block diagram. A recommended test

configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie

PLL_EN and REF_SEL together and connect them to the test select logic.

This functionality is needed since most board-level testers run at 1 MHz or

below, and theFCT 388915T cannot lock onto that low of an input frequency.

In the test mode described above, any test frequency test can be used.