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W25Q16VSFIG 数据表(PDF) 13 Page - Winbond |
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W25Q16VSFIG 数据表(HTML) 13 Page - Winbond |
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13 / 60 page  W25Q16V Publication Release Date: October 7, 2009 - 13 - Revision E 10.1.6 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down (1) Status Register is protected and can not be written to again until the next power-down, power-up cycle. (2) 1 1 X One Time Program (1) Status Register is permanently protected and can not be written to. Note: 1. These features are available upon special order. Please contact Winbond for details. 2. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 10.1.7 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins are tied directly to the power supply or ground. |
类似零件编号 - W25Q16VSFIG |
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类似说明 - W25Q16VSFIG |
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