数据搜索系统,热门电子元器件搜索 |
|
SI9166 数据表(PDF) 6 Page - Vishay Siliconix |
|
SI9166 数据表(HTML) 6 Page - Vishay Siliconix |
6 / 11 page Si9166 Vishay Siliconix www.vishay.com 6 Document Number: 70847 S-40701—Rev. C, 19-Apr-04 FUNCTIONAL BLOCK DIAGRAM Reference Threshold Generator Oscillator PSM Modulator PWM Modulator Soft-Start Timer UVLO POR Bias Generator Drivers PWM/PSM Select VDD SD GND PGND Positive Supply Negative Return and Substrate PWMEN PSMEN PWMIN PSMIN 0.5 V 1.0 V Ramp COSC VREF VO FB COMP SYNC ROSC PWM/PSM MODE DL DH VS SYSTEM MONITOR 1.3 V DETAIL OPERATIONAL DESCRIPTION Start-Up The UVLO circuit prevents the controller output driver and oscillator circuit from turning on, if the voltage on VDD pin is less than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is continuously powered on until the VDD voltage drops below 2.4 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal power-on-reset timer is activated while most circuitry, except the output driver, are turned on. After the POR time-out of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging the soft-start capacitor will force the converter output voltage to rise gradually without overshooting. To prevent negative undershoot, the synchronous switch is tri-stated until the duty cycle reaches about 10%. See start-up timing diagram. In tri-state, the high-side p-channel MOSFET is turned off by pulling up the gate voltage (DH) to VS potential. The low-side n-channel MOSFET is turned off by pulling down the gate voltage (DL) to PGND potential. Note that the Si9166 will always soft start in the PWM mode regardless of the voltage level on the PWM/PSM pin. Shutdown The Si9166 is designed to conserve battery life by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low-level on the SD pin, current consumption of the Si9166 decreases to less than 1 mA by shutting off most of the circuits. The logic high enables the controller and starts up as described in Start-Up section above. MODE Selection The Si9166 can be programmed to operate as Buck or Boost converter. If the MODE pin is connected to AGND, it operates in buck mode. If the MODE pin is connected to VDD, it operates in boost mode. The DH gate drive output is designed to drive high-side p-channel MOSFET, acting as the main switch in buck topology and the synchronous rectifier in boost topology. The DL gate drive output is designed to drive low-side n-channel MOSFET, acting as the synchronous rectifier in buck topology and the main switch in boost topology. |
类似零件编号 - SI9166 |
|
类似说明 - SI9166 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |