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MAX16071 Datasheet(数据表) 41 Page - Maxim Integrated Products

部件型号  MAX16071
说明  12-Channel/8-Channel, Flash-Configurable System Monitors with Nonvolatile Fault Registers
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制造商  MAXIM [Maxim Integrated Products]
网页  http://www.maxim-ic.com
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MAX16071 Datasheet(HTML) 41 Page - Maxim Integrated Products

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12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
______________________________________________________________________________________ 41
USERCODE: When the USERCODE instruction latches
into the parallel instruction register, the user-code data
register is selected. The device user-code loads into the
user-code data register on the rising edge of TCK fol-
lowing entry into the capture-DR state. Shift-DR can be
used to shift the user-code out serially through TDO. See
Table 25. This instruction can be used to help identify
multiple MAX16070/MAX16071 devices connected in a
JTAG chain.
LOAD ADDRESS: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16070/MAX16071. When the LOAD
ADDRESS instruction latches into the instruction register,
TDI connects to TDO through the 8-bit memory address
test data register during the shift-DR state.
READ DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16070/MAX16071. When the READ DATA
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory read test data
register during the shift-DR state.
WRITE DATA: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16070/MAX16071. When the WRITE DATA
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory write test data
register during the shift-DR state.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software-controlled
reset to the MAX16070/MAX16071. When the REBOOT
instruction latches into the instruction register, the
MAX16070/MAX16071 reset and immediately begin the
boot-up sequence.
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. The current ADC
conversion results along with fault information are saved
to flash depending on the configuration of the Critical
Fault Log Control register (r6Dh).
SETFLSHADD: This is an extension to the standard IEEE
1149.1 instruction set that allows access to the flash
page. Flash registers include ADC conversion results
and GPIO_ input/output data. Use this page to access
registers 200h to 2FFh
RSTFLSHADD: This is an extension to the standard
IEEE 1149.1 instruction set. Use RSTFLSHADD to return
to the default page and disable access to the flash page.
SETUSRFLSH: This is an extension to the standard IEEE
1149.1 instruction set that allows access to the user flash
page. When on the configuration flash page, send the
SETUSRFLSH command, all addresses are recognized
as flash addresses only. Use this page to access regis-
ters 300h to 3FFh.
RSTUSRFLSH: This is an extension to the standard IEEE
1149.1 instruction set. Use RSTUSRFLSH to return to the
configuration flash page and disable access to the user
flash.
Restrictions When Writing to Flash
Flash must be written to 8 bytes at a time. The initial
address must be aligned to 8-byte boundaries—the 3
LSBs of the initial address must be ‘000’. Write the 8
bytes using eight successive WRITE DATA commands.
Applications Information
Device Behavior at Power-Up
When VCC is ramped from 0, the RESET output is high
impedance until VCC reaches 1.4V, at which point RESET
goes low. All other outputs are high impedance until VCC
reaches 2.7V, when the flash contents are copied into
register memory. This takes 150Fs (max), after which the
outputs assume their programmed states.
Maintaining Power
During a Fault Condition
Power to the MAX16070/MAX16071 must be maintained
for a specific period of time to ensure a successful flash
fault log operation during a fault that removes power to
the circuit. Table 26 shows the amount of time required
depends on the settings in the fault control register
(r6Dh[1:0]).
Maintain power for shutdown during fault conditions in
applications where the always-on power supply cannot
be relied upon by placing a diode and a large capacitor
between the voltage source, VIN, and VCC (Figure 14).
Table 25. 32-Bit User-Code Data
MSB
LSB
Don’t Care
SMBus slave ID
User ID (r8Ah[7:0])
00000000000000000
See Table 20




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