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MAX16070 数据表(PDF) 11 Page - Maxim Integrated Products |
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MAX16070 数据表(HTML) 11 Page - Maxim Integrated Products |
11 / 52 page 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ______________________________________________________________________________________ 11 Detailed Description The MAX16070 monitors up to twelve system power sup- plies and the MAX16071 can monitor up to eight system power supplies. After boot-up, if EN is high and the soft- ware enable bit is set to ‘1,’ monitoring begins based on the configuration stored in flash. An internal multiplexer cycles through each MON_ input. At each multiplexer stop, the 10-bit ADC converts the monitored analog volt- age to a digital result and stores the result in a register. Each time a conversion cycle (50Fs, max) completes, internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. When a result violates a programmed threshold, the conversion can be configured to generate a fault. GPIO_ can be programmed to assert on combinations of faults. Additionally, faults can be configured to shut off the system and trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write-protects the data to prevent accidental erasure. The MAX16070/MAX16071 contain both SMBus and JTAG serial interfaces for accessing registers and flash. Use only one interface at any given time. For more infor- mation on how to access the internal memory through these interfaces, see the SMBus-Compatible Interface and JTAG Serial Interface sections. The memory map is divided into three pages with access controlled by special SMBus and JTAG commands. The factory-default values at POR (power-on reset) for all RAM registers are ‘0’s. POR occurs when VCC reaches the undervoltage-lockout threshold (UVLO) of 2.8V (max). At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and flash contents are copied to the respective register locations. During boot-up, the MAX16070/MAX16071 are not accessible through the serial interface. The boot-up sequence takes up to 150Fs, after which the device is ready for normal opera- tion. RESET is asserted low up to the boot-up phase and remains asserted for its programmed timeout period once sequencing is completed and all monitored channels are within their respective thresholds. Up to the boot-up phase, the GPIO_s are high impedance. Power Apply 2.8V to 14V to VCC to power the MAX16070/ MAX16071. Bypass VCC to ground with a 10FF capaci- tor. Two internal voltage regulators, ABP and DBP, supply power to the analog and digital circuitry within the device. For operation at 3.6V or lower, disable the regulators by connecting ABP and DBP to VCC. ABP is a 3.0V (typ) voltage regulator that powers the inter- nal analog circuitry. Bypass ABP to GND with a 1FF ceram- ic capacitor installed as close to the device as possible. DBP is an internal 3.0V (typ) voltage regulator. DBP pow- ers flash and digital circuitry. All push-pull outputs refer to DBP. Bypass the DBP output to GND with a 1FF ceramic capacitor installed as close as possible to the device. Do not power external circuitry from ABP or DBP. Enable To enable monitoring, the voltage at EN must be above 1.4V and the software enable bit in r73h[0] must be set to ‘1.’ To power down and disable monitoring, either pull EN below 1.35V or set the Software Enable bit to ‘0.’ See Table 1 for the software enable bit configurations. Connect EN to ABP if not used. Table 1. Software Enable Configurations REGISTER ADDRESS FLASH ADDRESS BIT RANGE DESCRIPTION 73h 273h [0] Software enable [1] Reserved [2] 1 = Margin mode enabled [3] Early warning threshold select 0 = Early warning is undervoltage 1 = Early warning is overvoltage [4] Independent watchdog mode enable 1 = Watchdog timer is independent of sequencer 0 = Watchdog timer boots after sequence completes |
类似零件编号 - MAX16070 |
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类似说明 - MAX16070 |
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