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LC88F40D0PAU 数据表(PDF) 6 Page - Sanyo Semicon Device

部件名 LC88F40D0PAU
功能描述  For Car Audio Systems 16-bit ETR Microcontroller
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制造商  SANYO [Sanyo Semicon Device]
网页  https://www.sanyo-av.com/us/
标志 SANYO - Sanyo Semicon Device

LC88F40D0PAU 数据表(HTML) 6 Page - Sanyo Semicon Device

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LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
No.A1853-6/32
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Both the XT oscillator and internal RC oscillator retain the state established when the standby mode is entered.
2) Both the XT and VCO clocks retain the state established when the standby mode is entered.
3) There are the two ways of releasing the HALT mode.
(1) Generating a reset condition
(2) Generating an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) Both the XT oscillator and internal RC oscillator automatically stop operation.
2) XT clock and VCO clock oscillators automatically stop.
3) There are the six ways of releasing the HOLD mode.
(1) Generating a reset condition
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt request generated in UART2, UART3, UART4, or UART5
(6) Having an interrupt request generated in SIO0 or SIO1
• HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run
on the XT clock.
1) The internal RC oscillator automatically stops operation.
2) The XT clock retains the state established when the HOLDX mode is entered and the VCO clock automatically
stops.
3) There are nine ways of resetting the HOLDX mode.
(1) Generating a reset condition
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at port 5
(5) Having an interrupt request generated in UART2, UART3, UART4, or UART5
(6) Having an interrupt request generated in SIO0 or SIO1
(7) Having an interrupt source established in the timer 8 circuit
(8) Having an interrupt source established in the infrared remote controller receive circuit
(9) Having an interrupt source established in the clock timer circuit
Reset
• External reset
• Voltage drop detection type of reset circuit (VDET circuit) incorporated
1) Normal mode detection voltage: 2.85V
±0.15V
2) HOLD mode detection voltage: 1.42V
±0.15V
On-chip debugger function
• Supports software debugging with the IC mounted on the target board.
• Supports source line debugging and tracing functions, and breakpoint setting and real time monitor.
• Single-wire communication
Shipping Form
• QIP100E (Lead free product)


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