 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
FM24VN05-GTR 数据表(PDF) 3 Page - Ramtron International Corporation |
|
||||||||||||||||||||||||||||||
FM24VN05-GTR 数据表(HTML) 3 Page - Ramtron International Corporation |
|
|
3 / 16 page  FM24V05 - 512Kb I2C FRAM Rev. 2.0 May 2010 Page 3 of 16 Overview The FM24V05 is a family of serial F-RAM memory devices. The memory array is logically organized as a 65,536 x 8 bit memory array and is accessed using an industry standard two-wire (I2C) interface. Functional operation of the F-RAM is similar to serial EEPROM. The major difference between the FM24V05 and serial EEPROM is F-RAM’s superior write performance. Memory Architecture When accessing the FM24V05, the user addresses 65,536 locations each with 8 data bits. These data bits are shifted serially. The 65,536 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other non-memory devices) and a 2-byte address. All 16 address bits are used by the decoder for accessing the memory. The access time for memory operation is essentially zero beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24V05 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that it is the user’s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. Two-wire Interface The FM24V05 employs a bi-directional two-wire bus protocol using few pins or board space. Figure 2 illustrates a typical system configuration using the FM24V05 in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24V05 always is a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including start, stop, data bit, or acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications section. Microcontroller SDA SCL FM24V05 A0 A1 A2 SDA SCL FM24V05 A0 A1 A2 VDD Rmin = 1.1 Kohm Rmax = tR/Cbus Figure 2. Typical System Configuration |
类似零件编号 - FM24VN05-GTR |
|
类似说明 - FM24VN05-GTR |
|
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
