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AM3872BCYE100 数据表(PDF) 1 Page - Texas Instruments

部件名 AM3872BCYE100
功能描述  AM387x Sitara ARM Microprocessors (MPUs)
Download  345 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

AM3872BCYE100 数据表(HTML) 1 Page - Texas Instruments

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AM3874, AM3872, AM3871
www.ti.com
SPRS695
– SEPTEMBER 2011
AM387x Sitara
ARM
® Microprocessors (MPUs)
Check for Samples: AM3874, AM3872, AM3871
1
High-Performance System-on-Chip (SoC)
1.1
Features
12
8-bit SD Capture Ports
• High-Performance Sitara™ ARM®
Microprocessors (MPUs)
One 8/16/24-bit Input
– Up to 1-GHz ARM® Cortex™-A8 RISC MPU
One 8-bit Only Input
• ARM® Cortex™-A8 Core
– Two 165 MHz HD Video Display Outputs
– ARMv7 Architecture
One 16/24/30-bit and one 16/24-bit Output
In-Order, Dual-Issue, Superscalar
– Composite or S-Video Analog Output
Microprocessor Core
– MacroVision® Support Available
NEON
™ Multimedia Architecture
– Digital HDMI 1.3 transmitter With Integrated
Supports Integer and Floating Point
PHY
Jazelle
® RCT Execution Environment
– Advanced Video Processing Features Such
as Scan/Format/Rate Conversion
• ARM® Cortex™-A8 Memory Architecture
– Three Graphics Layers and Compositors
– 32K-Byte Instruction and Data Caches
• Dual 32-bit LPDDR/DDR2/DDR3 SDRAM
– 512K-Byte L2 Cache
Interfaces
– 64K-Byte RAM, 48K-Byte Boot ROM
– Supports up to LPDDR-400, DDR2-800, and
• 128K-Bytes On-Chip Memory Controller
DDR3-800
(OCMC) RAM
– Up to Eight x 8 Devices Total 2 GB Total
• Imaging Subsystem (ISS)
Address Space
– Camera Sensor Connection
– Dynamic Memory Manager (DMM)
Parallel Connection for Raw (up to 16-Bit)
Programmable Multi-Zone Memory
and BT.656/BT.1120 (8-/16-bit)
Mapping and Interleaving
– Image Sensor Interface (ISIF) for Handling
Enables Efficient 2D Block Accesses
Image/Video Data From the Camera Sensor
Supports Tiled Objects in 0
°, 90°, 180°, or
– Resizer
270
° Orientation and Mirroring
Resizing Image/Video From 1/16x to 8x
Optimizes Interlaced Accesses
Generating Two Different Resizing
• General Purpose Memory Controller (GPMC)
Outputs Concurrently
– 8-/16-bit Multiplexed Address/Data Bus
• Media Controller
– 512M-Byte Total Address Space Divided
– Controls the HDVPSS and ISS
Among up to 8 Chip Selects
• SGX530 3D Graphics Engine
– Glueless Interface to NOR Flash, NAND
– Delivers up to 18 MPoly/sec
Flash (BCH/Hamming Error Code Detection),
– Universal Scalable Shader Engine
SRAM and Pseudo-SRAM
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
– Error Locator Module (ELM) Outside of
OpenVG 1.0, OpenMax API Support
GPMC to Provide Upto 16-Bit/512-Bytes
– Advanced Geometry DMA Driven Operation
Hardware ECC for NAND
– Programmable HQ Image Anti-Aliasing
– Flexible Asynchronous Protocol Control for
• Endianness
Interface to FPGA, CPLD, ASICs, etc.
– ARM Instructions/Data – Little Endian
• Enhanced Direct-Memory-Access (EDMA)
Controller
• HD Video Processing Subsystem (HDVPSS)
– Four Transfer Controllers
– Two 165 MHz HD Video Capture Inputs
– 64/8 Independent DMA/QDMA Channels
One 16/24-bit Input, Splittable into Dual
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative
Copyright
© 2011, Texas Instruments Incorporated
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.


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