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DAC34H84IZAY 数据表(PDF) 5 Page - Texas Instruments

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部件名 DAC34H84IZAY
功能描述  Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

DAC34H84IZAY 数据表(HTML) 5 Page - Texas Instruments

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DAC34H84
www.ti.com
SLAS751B
– MARCH 2011 – REVISED SEPTEMBER 2011
PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
A10, A13,
A14, B10,
B11, B12,
B13, C5, C6,
C7, C8, C9,
C10, C13,
D8, D13,
D14, E8,
E12, E13,
F6, F7, F8,
F9, F12, F13,
G6, G7, G8,
GND
G9, G13,
I
These pins are ground for all supplies.
G14, H6, H7,
H8, H9, H13,
H14, J6, J7,
J8, J9, J12,
J13, K8, K13,
L8, L13, L14,
M5, M6, M7,
M8, M9,
M10, M11,
M12, M13,
N13, P13,
P14
IOUTAP
B14
O
A-Channel DAC current output. Connect directly to ground if unused.
IOUTAN
C14
O
A-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTBP
F14
O
B-Channel DAC current output. Connect directly to ground if unused.
IOUTBN
E14
O
B-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTCP
J14
O
C-Channel DAC current output. Connect directly to ground if unused.
IOUTCN
K14
O
C-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTDP
N14
O
D-Channel DAC current output. Connect directly to ground if unused.
IOUTDN
M14
O
D-Channel DAC complementary current output. Connect directly to ground if unused.
D5, D6, G5,
IOVDD
I
Supply voltage for all LVDS I/O. (3.3 V)
H5, L5. L6
Supply voltage for all CMOS I/O. (1.8 to 3.3V) This supply can range from 1.8V to 3.3V to change the
IOVDD2
L12
I
input and output level of the CMOS I/O.
LPF
D12
I/O
PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected.
Optional LVPECL output strobe positive input. This positive/negative pair is captured with the rising
OSTRP
A9
I
edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in Dual Sync
Sources Mode. If unused it can be left unconnected.
OSTRN
B9
I
Optional LVPECL output strobe negative input. (See the OSTRP description)
Optional LVDS positive input parity bit for the CD-data bus. The PARITYCDP/N LVDS pair has an
internal 100
Ω termination resistor. If unused it can be left unconnected.
PARITYCDP
N8
I
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface
when setting the rev_interface bit in register config1.
PARITYCDN
P8
I
Optional LVDS negative input parity bit for the CD-data bus.
PLLAVDD
C11, D11
I
PLL analog supply voltage. (3.3 V)
SCLK
P9
I
Serial interface clock. Internal pull-down.
SDENB
P10
I
Active low serial data enable, always an input to the DAC34H84. Internal pull-up.
Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional 4-pin mode. Internal
SDIO
P11
1/O
pull-down.
Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode
SDO
P12
O
(default).
SLEEP
N11
I
Active high asynchronous hardware power-down input. Internal pull-down.
Copyright
© 2011, Texas Instruments Incorporated
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