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DRV8302DCAR Datasheet(数据表) 8 Page - Texas Instruments

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部件型号  DRV8302DCAR
说明  Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator Hardware Controlled
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DRV8302DCAR Datasheet(HTML) 8 Page - Texas Instruments

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DRV8302
SLES267
– AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
PVDD = 8-60 V, TC = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
VGX_NORM
Gate driver Vgs voltage
PVDD = 8
–60V
9.5
11.5
V
Ioso1
Maximum source current setting 1, peak
Vgs of FET equals to 2 V. REG 0x02
1.7
A
Iosi1
Maximum sink current setting 1, peak
Vgs of FET equals to 8 V. REG 0x02
2.3
A
Gate output impedence during standby mode
Rgate_off
1.6
2.4
k
Ω
when EN_GATE low (pins GH_x, GL_x)
SUPPLY CURRENTS
IPVDD1_STB
PVDD1 supply current, standby
EN_GATE is low. PVDD1 = 8V.
20
50
µA
EN_GATE is high, no load on gate drive
output, switching at 10 kHz,
IPVDD1_OP
PVDD1 supply current, operating
15
mA
100 nC gate charge
IPVDD1_HIZ
PVDD1 Supply current, HiZ
EN_GATE is high, gate not switching
2
5
11
mA
INTERNAL REGULATOR VOLTAGE
AVDD
AVDD voltage
6
6.5
7
V
DVDD
DVDD voltage
3
3.3
3.6
V
VOLTAGE PROTECTION
VPVDD_UV
Under voltage protection limit, PVDD
6
V
VGVDD_UV
Under voltage protection limit, GVDD
8
V
VGVDD_OV
Over voltage protection limit, GVDD
16
V
CURRENT PROTECTION, (VDS SENSING)
VDS_OC
Drain-source voltage protection limit
0.125
2.4
V
Toc
OC sensing response time
1.5
µs
OCTW pin reporting pulse stretch length for OC
TOC_PULSE
64
µs
event
8
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Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): DRV8302




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