8

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FN6072.9

April 13, 2011

ISL45042 Truth Table

The ISL45042 truth table is shown in Table 2. For proper

operation the CE should be disabled (pulled low) before

powering the device down to assure that the glitches and

transients will not cause unwanted EEPROM overwriting.

.

TABLE 2. TRUTH TABLE

INPUT

OUTPUT

CTL

CE

VDD

OUT

ICC

MEMORY

Mid to Hi

Hi

VDD

Increment

Normal

X

Mid to Lo

Hi

VDD

Decrement

Normal

X

X

Lo

VDD

No Change Increased

Read

>4.9V

Hi

VDD

No Change Increased

Program

CTL LOW

CTL HIGH

CE

78

79

7A

7B

7A

UNDEF.

COUNTER

OUTPUT

FIGURE 8. ISL45042 TIMING DIAGRAM

VCOM

IGNORES 1ST PULSE

AFTER PROGRAMMING

STOP PROGRAMMING

AFTER POWER IS 1ST APPLIED,

THE VERY 1ST CTL PULSE IS IGNORED

THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING.

NOTE:

START PROGRAMMING

START PROGRAMMING

ISL45042