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TMP103AYFFR 数据表(PDF) 9 Page - Texas Instruments

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部件名 TMP103AYFFR
功能描述  Low-Power, Digital Temperature Sensor with Two-Wire Interface in WCSP
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMP103AYFFR 数据表(HTML) 9 Page - Texas Instruments

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TMP103
www.ti.com
SBOS545A
– FEBRUARY 2011 – REVISED MARCH 2011
Table 7. THIGH Register
ONE-SHOT (M1 =
'0', M0 = '1')
D7
D6
D5
D4
D3
D2
D1
D0
The TMP103 features a One-Shot Temperature
H7
H6
H5
H4
H3
H2
H1
H0
Measurement mode. When the device is in Shutdown
mode, writing a '01' to bits M1 and M0 starts a single
temperature conversion. During the conversion, bits
Table 8. TLOW Register
M1 and M0 read '01'. The device returns to the
D7
D6
D5
D4
D3
D2
D1
D0
shutdown state at the completion of the single
L7
L6
L5
L4
L3
L2
L1
L0
conversion. After the conversion, bits M1 and M0
read '00'. This feature is useful for reducing power
consumption
in
the
TMP103
when
continuous
BUS OVERVIEW
temperature monitoring is not required.
The device that initiates the transfer is called a
As a result of the short conversion time, the TMP103
master, and the devices controlled by the master are
can achieve a higher conversion rate. A single
slaves. The bus must be controlled by a master
conversion typically takes 26ms and a read can take
device that generates the serial clock (SCL), controls
place in less than 20
μs. When using One-Shot mode,
the bus access, and generates the START and STOP
30 or more conversions per second are possible.
conditions.
To address a specific device, a START condition is
CONTINUOUS CONVERSION MODE (M1 =
'1')
initiated, indicated by pulling the data line (SDA) from
When the TMP103 is in Continuous Conversion mode
a high to low logic level while SCL is high. All slaves
(M1 = '1'), a single conversion is performed at a rate
on the bus shift in the slave address byte on the
determined by the conversion rate bits, CR1 and CR0
rising edge of the clock, with the last bit indicating
(in
the
Configuration
Register).
The
TMP103
whether a read or write operation is intended. During
performs a single conversion and then powers down
the ninth clock pulse, the slave being addressed
and waits for the appropriate delay set by CR1 and
responds
to
the
master
by
generating
an
CR0. See Table 6 for CR1 and CR0 settings.
Acknowledge and pulling SDA low.
Data transfer is then initiated and sent over eight
TEMPERATURE LIMIT REGISTERS
clock pulses followed by an Acknowledge Bit. During
The THIGH and TLOW registers are used to store the
data transfer, SDA must remain stable while SCL is
temperature
limit
thresholds
for
the
TMP103
high, because any change in SDA while SCL is high
watchdog function. At the end of each temperature
is interpreted as a START or STOP signal.
measurement,
the
TMP103
compares
the
Once all data have been transferred, the master
temperature results to each of these limits. If the
generates a STOP condition indicated by pulling SDA
temperature result is greater than the THIGH limit, then
from low to high, while SCL is high.
the FH bit in the configuration register is set to '1'. If
the temperature result is less than the TLOW limit, then
SERIAL INTERFACE
the FL bit in the configuration register is set to '1'; see
Figure 8.
The TMP103 operates as a slave device only on the
two-wire bus and SMBus. Connections to the bus are
Table 7 and Table 8 describe the format for the THIGH
made via the open-drain I/O lines SDA and SCL. The
and TLOW registers. Power-up reset values for THIGH
SDA
and
SCL
pins
feature
integrated
spike
and TLOW are: THIGH = +60°C and TLOW = –10°C. The
suppression filters and Schmitt triggers to minimize
format of the data for THIGH and TLOW is the same as
the effects of input spikes and bus noise. The
for the Temperature Register.
TMP103 supports the transmission protocol for both
fast (1kHz to 400kHz) and high-speed (1kHz to
3.4MHz) modes. All data bytes are transmitted MSB
first.
Copyright
© 2011, Texas Instruments Incorporated
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