ISLA212P50

11

FN7843.1

May 25, 2011

CLKDIVRSTP Input Pull-down Resistance

100

kΩ

CLKDIVRSTN Input Pull-up Resistance

100

kΩ

LVDS OUTPUTS

Differential Output Voltage (Note 10)

3mA Mode

612

Output Offset Voltage

3mA Mode

1120

1150

1200

mV

Output Rise Time

240

ps

Output Fall Time

240

ps

CMOS OUTPUTS

Voltage Output High

OVDD - 0.3 OVDD - 0.1

V

Voltage Output Low

0.1

0.3

V

Output Rise Time

1.8

ns

Output Fall Time

1.4

ns

NOTES:

9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending

on desired function.

10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.

PARAMETER

SYMBOL

CONDITIONS

MIN

(Note 5)

TYP

MAX

(Note 5)

UNITS

PARAMETER

SYMBOL

CONDITIONS

MIN

(Note 5)

TYP

MAX

(Note 5)

UNITS

Offset Mismatch-induced Spurious Power

No I2E Calibration performed

-65

dBFS

Active Run state enabled

-70

dBFS

I2E Settling Times

I2Epost_t

Calibration settling time for

Active Run state

1000

ms

Minimum Duration of Valid Analog Input

Allow one I2E iteration of Offset,

Gain and Phase correction

100

µs

Largest Interleave Spur

Run State enabled, in Track Mode

-99

dBc

Run State enabled and previously

settled, in Hold Mode

-75

-80

dBc

Run State enabled, in Track Mode

-99

dBc

Run State enabled and previously

settled, in Hold Mode

-75

dBc

Total Interleave Spurious Power

Active Run State enabled, in

-85

dBc

Active Run State enabled, in

-75

dBc

Sample Time Mismatch Between Unit ADCs

Active Run State enabled, in

Track Mode

25

fs

Gain Mismatch Between Unit ADCs

0.01

%FS

Offset Mismatch Between Unit ADCs

1mV