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ADM1276-3ACPZ-RL 数据表(PDF) 7 Page - Analog Devices |
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ADM1276-3ACPZ-RL 数据表(HTML) 7 Page - Analog Devices |
7 / 48 page ADM1276 Rev. 0 | Page 7 of 48 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Address Set to 11 2 V Connect to VCAP Input Current for Address 11 3 10 μA VADR = 2.0 V to VCAP; must not exceed the maximum allowable current draw from VCAP SERIAL BUS DIGITAL INPUTS (SDA, SCL) Input High Voltage VIH 1.1 V Input Low Voltage VIL 0.8 V Output Low Voltage VOL 0.4 V IOL = 4 mA Input Leakage ILEAK-PIN −10 +10 μA −5 +5 μA Device is not powered Nominal Bus Voltage VDD 2.7 5.5 V 3 V to 5 V ± 10% Capacitance for SDA, SCL Pins CPIN 5 pF Input Glitch Filter tSP 0 50 ns SERIAL BUS TIMING CHARACTERISTICS Table 2. Parameter Description Min Typ Max Unit Test Conditions/Comments fSCLK Clock frequency 400 kHz tBUF Bus free time 1.3 μs Following the stop condition of a read transaction 4.7 μs Following the stop condition of a write transaction tHD;STA Start hold time 0.6 μs tSU;STA Start setup time 0.6 μs tSU;STO Stop setup time 0.6 μs tHD;DAT SDA hold time 300 900 ns tSU;DAT SDA setup time 100 ns tLOW SCL low time 1.3 μs tHIGH SCL high time 0.6 μs tR SCL, SDA rise time 20 300 ns tF SCL, SDA fall time 20 300 ns Timing Diagram tLOW tBUF tHD;DAT tSU;DAT tSU;STA tHD;STA tHIGH tR tF tSU;STO P S S P VIH VIL VIH VIL SCL SDA Figure 2. Serial Bus Timing Diagram |
类似零件编号 - ADM1276-3ACPZ-RL |
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类似说明 - ADM1276-3ACPZ-RL |
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