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FAN2560UC13X 数据表(PDF) 2 Page - Fairchild Semiconductor |
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FAN2560UC13X 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 11 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2560 • Rev. 1.0.1 2 Block Diagram Figure 3. IC Block Diagram Pin Configuration VIN VBAT VOUT EN B2 A3 C1 C3 A1 GND TOP VIEW B2 A3 A1 C3 C1 VOUT EN VIN VBAT GND BOTTOM VIEW Figure 4. 0.96 x 1.33mm WLCSP package Pin Definitions Pin # Name Description A1 VIN Power supply input. A minimum 1 μF MLCC is required to GND. A3 VOUT Output Voltage. A typical COUT=1μF to 2.2μF MLCC is required to GND, placed close to the VOUT terminal. C1 VBAT Battery bias supply input. No capacitor is required unless another bulk capacitor is more than few inches away. C3 EN Enable input. The device is in shutdown mode when the voltage at this pin is <0.4V and enabled when >1.1V. The EN latches the LOW logic state once externally forced. Do not leave this pin floating when the device is turned ON. B2 GND Ground pin. Connect to a PCB GND plane. |
类似零件编号 - FAN2560UC13X |
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类似说明 - FAN2560UC13X |
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