AN-6982

APPLICATION NOTE

© 2010 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.0 • 6/8/10

5

Soft-Start Function

The soft-start is combined with RDY pin operation. During

startup, the RDY pin remains floating until the PFC output

voltage reaches 96% of its nominal value. When the supply

voltage of the downstream converter is controlled by the

RDY pin, the PFC stage starts with no load since the

downstream converter does not operate until the PFC

output voltage is built to a certain level.

HIGH during the startup since the actual output voltage is

until the PFC output voltage reaches its target value. Once

the PFC output reaches its target value, the error amplifier

comes out of saturation. However, it takes several line

regulation, which delivers more power to the load than

required, causing output voltage overshoot.

To prevent output voltage overshoot during startup caused

by the saturation of error amplifier; FAN6982 clamps the

of its maximum value, until PFC output reaches 96% of its

nominal value. Once the PFC output voltage reaches 96%

disabled. Then the voltage of PFC output is regulated by

voltage control loop.

Nominal Output Voltage

96% of Nominal Output Voltage

2.8V

SAT

Input Line Current

Figure 12.

PFC Soft-Start