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K8P2815UQC

datasheet

FLASH MEMORY

Rev. 1.0

10.16 Hardware Reset

is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. If a hardware reset

occurs during a program operation, the data at that particular location will be lost. Once the RESET pin is taken high, the device requires 200ns of wake-

up time until outputs are valid for read access. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse.

The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the device will be automati-

cally reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory.

10.17 Power-up Protection

To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the

read mode.

10.18 Low Vcc Write Inhibit

age), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subse-

′s responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when Vcc is above 2.3V.

10.19 Write Pulse Glitch Protection

Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.

10.20 Logical Inhibit

"1".

10.21 Commom Flash Memory Interface

Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device,

such as memory size, word configuration, and electrical features. Once this information has been obtained, the system software will know which com-

mand sets to use to enable flash writes, block erases, and control the flash component.

When the system writes the CFI command(98H) to address 55H in word mode, the device enters the CFI mode. And then if the system writes the

address shown in Table 8, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In

word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.

10.22 OTP Block Region

The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN).

The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. Indicator

bits DQ6 and DQ7 are used to indicate the factory-locked and customer locked status of the part. The data is DQ6 = "1" for customer locked and DQ7 =

"1" for factory locked.

The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 6). After the

system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (000000h~0000FFh) normally and

may check the Protection Verify Bit (DQ7,DQ6) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This

mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the

device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and

unlock bypass modes are not available when the OTP Block is enabled.

10.22.1 Customer Lockable

In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and

Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP

Block" Command sequence, and it can be permanently locked to "1" by issuing the OTP Protection bit program Command sqeunce. Once the OTP block

is locked and verified, the system must write the Exit OTP block command to return to reading and writing the remainder of the array.

10.22.2 OTP Protection Bits

OTP protection bits prevent programming of the OTP block memory area. Once set, the OTP area are non-modifiable.

• The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block

space can be modified in any way.

• Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operation.