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LC89515 数据表(PDF) 5 Page - Sanyo Semicon Device |
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LC89515 数据表(HTML) 5 Page - Sanyo Semicon Device |
5 / 6 page Write Note: The values of the shaded bits are ignored. 6. Additional Registers Write [R14] CTRL2: Control 2 STENCTL (STEN control) 0.........The external STEN pin goes to 0 when the microprocessor writes one byte of status information. (This is identical to LC8951 operation.) 1.........The external STEN pin goes to 0 due to 0 being written to the STENTRG register when the microprocessor writes * bytes of status information. This bit is set to 0 on reset. STENTRG (STEN trigger) This bit is only valid when STENCTL is 1. The external STEN pin goes to 0 when a 0 is written to this bit. This bit is reset when the host reads the last byte, i.e., when the external STEN pin has become 1. DLAEN (drive last address enable) When WRRQ is set to 0 during buffering, buffering continues until the next SYNC signal arrives and then stops. This results in the sectors that are buffered when WRRQ was set to 0 becoming valid. (This bit is set to 0 on reset.) BCKSL (bit clock select) Setting this bit to 1 allows the bit clock from the CD-DSP to be inverted. (SDATA is acquired on the rising edge of BCK.) (This bit is set to 0 on reset.) No. 4272-5/6 LC89515K RS AR No. Symbol BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 — — AR A3 A2 A1 A0 0000 R0 SBOUT msb — — — — — — lsb 0001 R1 IFCTRL CMDIEN DTEIEN DECIEN CMDBK DTWAI STWAI DOUTEN SOUTEN 0010 R2 DBCL B7 B6 B5 B4 B3 B2 B1 B0 0011 R3 DBCH B11 B10 B9 B8 0100 R4 DACL A7 A6 A5 A4 A3 A2 A1 A0 0101 R5 DACH A15 A14 A13 A12 A11 A10 A9 A8 0110 R6 DTTRG 1 0111 R7 DTACK 1000 R8 WAL A7 A6 A5 A4 A3 A2 A1 A0 1001 R9 WAH A15 A14 A13 A12 A11 A10 A9 A8 1010 R10 CTRL0 DECEN E01RQ AUTORQ ERAMRQ WRRQ QRQ PRQ 1011 R11 CTRL1 SYIEN SYDEN DSCREN COWREN MODRQ FORMRQ MBCKRQ SHDREN 1100 R12 PTL A7 A6 A5 A4 A3 A2 A1 A0 1101 R13 PTH A15 A14 A13 A12 A11 A10 A9 A8 1110 R14 CTRL2 0 0 0 BCKSL DLAEN 0 STENCTL STENTRG 1111 R15 RESET |
类似零件编号 - LC89515 |
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类似说明 - LC89515 |
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