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LC877264A 数据表(PDF) 10 Page - Sanyo Semicon Device |
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LC877264A 数据表(HTML) 10 Page - Sanyo Semicon Device |
10 / 24 page LC877264A/56A/48A No.6719-10/24 Port Configuration Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Terminal Option applies to: Options Output Form Pull-up resistor 1 CMOS Programmable (Note 1) P00 to P07 each bit 2 Nch-open drain None 1 CMOS Programmable P10 to P17 each bit 2 Nch-open drain Programmable 1 CMOS Programmable P30 to P35 each bit 2 Nch-open drain None P70 – None Nch-open drain Programmable P71 to P73 – None CMOS Programmable P80 to P87 – None Nch-open drain None S0/PA0 to S47/PF7 – None CMOS Programmable COM0/PL0 to COM3/PL3 – None Input only None V1/PL4 to V3/PL6 – None Input only None XT1 – None Input only None XT2 – None Output for 32.768kHz crystal oscillation None Note 1 Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07). * Note 1: Connect as follows to reduce noise on VDD. VSS1, VSS2 and VSS3 must be connected together and grounded. *Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD3 as the power supply for ports. When the VDD3 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when the VDD3 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD3 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. LSI VDD1 Back-up capacitors *2 VDD2 VDD3 VSS2 VSS1 Power supply VSS3 |
类似零件编号 - LC877264A |
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类似说明 - LC877264A |
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