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LC867224 数据表(PDF) 8 Page - Sanyo Semicon Device

部件名 LC867224
功能描述  8-Bit Single Chip Microcontroller with the UVEPROM
Download  19 Pages
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制造商  SANYO [Sanyo Semicon Device]
网页  https://www.sanyo-av.com/us/
标志 SANYO - Sanyo Semicon Device

LC867224 数据表(HTML) 8 Page - Sanyo Semicon Device

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LC86E7248
No.6749-8/19
Pin name
I/O
Function description
Option
PROM mode
Port A
(S0/PA0 –
S7/PA7)
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output
port
-
Address input
A0 to A7
Port B
(S8/PB0 –
S15/PB7)
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output
port
-
Address input
A8 to A13
Port C
(S16/PC0 –
S23/PC7)
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output
port
-
PROM control
signal input
• TA (*5)
Address input
• A14, A15
Port D
(S24/PD0 –
S31/PD7)
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output
port
-
-
Port E
(S32/PE0 –
S39/PE7)
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output
port
-
-
Port F
(S40/PF0 –
S47/PF7)
I/O
• Segment output terminal for LCD display
• Can be used as a general input/output
port
-
-
Port L
(COM0/PL0
COM3/PL3)
I/O
• Common output terminal for LCD display
• Can be used as a general input port
-
-
V1/PL4 –
V3/PL6
I
• Bias power terminal for LCD drive
• Can be used as a general input port
-
-
RES
I
Reset pin
-
-
XT1/ P74
I
• Input pin for 32.768kHz crystal
oscillation
In case of non use, connect to VDD.
• Other function
A general input port P74
-
-
XT2/P75
O
(I)
• Output pin for 32.768kHz crystal
oscillation
In case of non use, should be left
unconnected
• Other function
A general input port P75
-
-
CF1
I
Input pin for ceramic resonator
oscillation
-
-
CF2
O
Output pin for ceramic resonator
oscillation
-
-
* All of port options can be specified in a bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM control signal input
Power
Supply
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
LSI


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