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LC7930N 数据表(PDF) 5 Page - Sanyo Semicon Device |
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LC7930N 数据表(HTML) 5 Page - Sanyo Semicon Device |
5 / 7 page Pin Descriptions Pin Name Function VDD Logic circuitry power supply (+5 V ±10%) VSS 0V VEE LCD driver power supply (–4 to –6 V) Y1 to Y20 Channel 1 LCD driver output pins Y21 to Y40 Channel 2 LCD driver output pins V1, V2 Reference voltage for selected driver outputs V3, V4 Reference voltage for non-selected driver outputs (channel 1) V5, V6 Reference voltage for non-selected driver outputs (channel 2) L/R1 Shift direction for channel 1 shift register L/R2 Shift direction for channel 2 shift register LDATA1 RDATA1 Serial data input/output pins for channel 1 shift register LDATA2 RDATA2 Serial data input/output pins for channel 2 shift register M Switching clock signal for LCD driver. CLKLA Latches channael 1 data on the falling edge. This also will latch channel 2 data on the falling edge if CH2-BP is low. CLKSR Shift channel 1 data on the falling edge. This also will shift channel 2 data on the falling edge if CH2-BP is low. CH2-BP Switches the mode of channel 2. Exchanges the latch signal for the shift signal of channel 2 and invert the M signal. Channel 2, then, can be used as a scan-line driver. L/R1 LDATA1 RDATA1 High-level Output Input Low-level Input Output L/R2 LDATA2 RDATA2 High-level Output Input Low-level Input Output CH2-BP Channel 2 M Latch Shift High CLKSR CLKLA M For scan-line driver Low CLKLA CLKSR M For signal line driver Functional Description LC7930N, LC7930NW are serial data transfer type LCD drivers. Data inputted serially from the data pin is shifted successively by the synchronizing clock (CLKSR) and latched by the latch clock (CLKLA) when the all data are shifted. . Segment terminal When CH2-BP goes to low, the data of channel 1 and channel 2 are shifted at the falling edge of CLKSR, and then latched at the falling edge of the CLKLA. The reference pulse will be switched to selected or unselected due to the latched data. . Scan terminal When CH2-BP goes to high, the data of channel 2 is shifted at the rising edge of CLKLA, and then latched at the rising edge of the CLKSR. When FLM signal, as a data, is inputted, the output will be scan terminal drive mode. Continued on next page. LC7930N, 7930NW No.2778-5/7 |
类似零件编号 - LC7930N |
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类似说明 - LC7930N |
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