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LC75817NW 数据表(PDF) 9 Page - Sanyo Semicon Device

部件名 LC75817NW
功能描述  1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function
Download  43 Pages
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制造商  SANYO [Sanyo Semicon Device]
网页  https://www.sanyo-av.com/us/
标志 SANYO - Sanyo Semicon Device

LC75817NW 数据表(HTML) 9 Page - Sanyo Semicon Device

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No. 6144-9/43
LC75817NE, 75817NW
• ADRAM (Additional data RAM)
ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 12
× 5 bits, and the stored
display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence
between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.
When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12)
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
ADRAM address (hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
ADRAM address (hexadecimal)
1
2
3
4
5
6
7
8
9
A
B
0
(Shift left)
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
ADRAM address (hexadecimal)
B
0
1
2
3
4
5
6
7
8
9
A
(Shift right)
Note: *5. The ADRAM address is expressed in hexadecimal.
Example: When the ADRAM address is AH
Note: *6. 5
× 7 dots ... 12-digit display
5 dots
5
× 8 dots ... 12-digit display
5 dots
5
× 9 dots ... 12-digit display
4 dots
• CGROM (Character generator ROM)
CGROM is ROM that is used to generate the 240 kinds of 5
× 7, 5 × 8, or 5 × 9 dot matrix character patterns from the
8-bit character codes. CGROM has a capacity of 240
× 45 bits. When a character code is written to DCRAM, the
character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD
corresponding to the DCRAM address loaded into AC.
• CGRAM (Character generator RAM)
CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5
× 7, 5 × 8,
or 5
× 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits.
ADRAM address
RA0
RA1
RA2
RA3
RA0
RA1
RA2
RA3
0
1
0
1
Hexadecimal
Least significant bit
LSB
Most significant bit
MSB


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