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LC72710W 数据表(PDF) 9 Page - Sanyo Semicon Device

部件名 LC72710W
功能描述  Mobile FM Multiplex Broadcast DARC Receiver IC with On-Chip VICS Decoder
Download  33 Pages
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制造商  SANYO [Sanyo Semicon Device]
网页  https://www.sanyo-av.com/us/
标志 SANYO - Sanyo Semicon Device

LC72710W 数据表(HTML) 9 Page - Sanyo Semicon Device

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No. 6166-9/33
LC72710W, 72710LW
Pin Functions
Pin No.
Pin
Function
I/O
Pin circuit
Data bus I/O control 1 (SP = low)*1
Data bus I/O control 2 (SP = low)*1
DMA acknowledge (SP = low)*1
Write control signal (SP = low)*1
Read control signal (SP = low)*1
Address input 0 (SP = low) CCB CL input (SP = high)
1 (SP = low) CCB CE input (SP = high)
2 (SP = low) CCB DI input (SP = high)
3 (SP = low)*1
Chip select input (SP = L)*1
System reset input (negative logic)
Standby mode (positive logic)
3
4
13
38
39
40
41
42
43
44
46
45
IOCNT1
IOCNT2
DACK
WR
RD
A0/CL
A1/CE
A2/DI
A3
CS
RST
STNBY
SP = low: parallel, SP = high: serial
BUSWD = low: 8 bits, BUSWD = high: 16 bits
The test pin must be connected to the digital system ground (VSS).
Must be connected to the digital system power supply (VDD) or ground
(VSS) in normal operation.
As above
As above
As above
As above
47
48
60
58
59
61
62
49
SP
BUSWD
TEST
TPC1
TPC2
TOSEL1
TOSEL2
TIN
Clock regeneration monitor
Demodulated data monitor
5
6
CLK16
DATA
Frame start signal output
Block start signal output
Outputs a high level during frame synchronization
Outputs a high level during block synchronization
Level 4 CRC detection result output
9
10
7
8
11
FCK
BCK
FLOCK
BLOCK
CRC4
External CPU interrupt request output
DMA request signal
Read ready signal
Input
Input
Output
I/O
33
12
16
INT
DREQ
RDY
Data bus
The bus width can be set to be either 8 bits or 16 bits by the BUSWD
pin (pin 48).
For data input, only the lower 8 bits (D0 to D7) are valid.
17 to 24
D0 to D7
Output
Data bus (in 16-bit mode)
These pins are held in the output off state when BUSWD is low.
25 to 32
D8 to D15
I/O
Connections for the system clock crystal oscillator circuit.
The XIN pin can also be used as an external clock signal input.
64
1
XIN
XOUT
Input
Baseband (multiplex) signal input
53
MPXIN
+
Output
Subcarrier output (76 kHz bandpass filter output)
55
FLOUT
Continued on next page.


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