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LC72336 数据表(PDF) 6 Page - Sanyo Semicon Device |
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LC72336 数据表(HTML) 6 Page - Sanyo Semicon Device |
6 / 16 page Note: 1. Except for the divider resistors used for the bias voltage generation circuit incorporated in the Vdd1 and Vdd2 systems. Test Circuits Figure 1 IDD2, IDD3, and IDD4 in Hold Mode Figure 2 IDD5 in Backup Mode Pin Functions No. 5157-6/16 LC72336, 72338 Pin No. Symbol I/O I/O type Function 18 17 16 15 14 13 12 11 10 9 8 7 PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 I O Inputs with pull-down resistors Unbalanced CMOS push-pull circuits These are special-purpose ports for key return signal inputs. Their threshold voltage is set lower than that of other inputs. When a key matrix is formed in conjunction with ports PB and PC, up to three simultaneous key presses can be detected. The pull-down resistors are set up for all four pins by the IOS instruction (Pn = 2, b1). This cannot be specified on an individual pin basis. Input is disabled in clock stop mode. These are special-purpose ports for key return signal outputs. No diodes for preventing short-circuits due to multiple simultaneous key presses are required since the output transistor circuits are unbalanced CMOS circuits. These pins become high-impedance outputs in clock stop mode. These pins function as high-impedance outputs after a power-on reset and retain that state until an output instruction is executed. Continued on next page. Note: With all ports other than those indicated in the figure open. With the segment port function selected for ports PE, PF, PM, and PN. With the output function selected for ports PG and PK. Note: With all ports other than those indicated in the figure open. With the segment port function selected for ports PE, PF, PM, and PN. With the output function selected for ports PG and PK. To the common and segment drivers The loss due to these resistor is excluded Vdd1 Vdd2 |
类似零件编号 - LC72336 |
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类似说明 - LC72336 |
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