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FM25Q16 数据表(PDF) 11 Page - FIDELIX |
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FM25Q16 数据表(HTML) 11 Page - FIDELIX |
11 / 62 page Rev.06 (Aug.18. 2010) 11 FM25Q16 10. FUNCTIONAL DESCRIPTION 10.1 SPI OPERATIONS 10.1.1 Standard SPI Instructions The FM25Q16 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK). Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising edges of /CS. 10.1.2 Dual SPI Instructions The FM25Q16 supports Dual SPI operation when using the “Fast Read Dual I/O” (BB hex) instruction. This instruction allows data to be transferred to or from the device at three to four the rate ordinary Serial Flash devices. The Dual Read instruction is ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins become bidirectional I/0 pins; IO0 and IO1. 10.1.3 Quad SPI Instructions The FM25Q16 supports Quad SPI operation when using the “Fast Read Quad I/O” (EB hex). This instruction allows data to be transferred to or from the device six to seven times the rate of ordinary Serial Flash. The Quad Read instruction offers a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instruction the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 10.1.4 Hold Function The /HOLD pin is used to pause a serial sequence of the SPI flash memory without resetting the clocking sequence. To activate the /HOLD mode, the /CS must be in active low state. The /HOLD mode begins when the CLK in active low state coincides with the falling edge of the /HOLD signal. The HOLD mode ends when the /HOLD signal’s rising edge coincides with the CLK in active low state. If the falling edge of the /HOLD signal does not coincide with the CLK in active low state, then the device enters HOLD mode when the CLK reaches the next active low state. Similarly, if the rising edge of the /HOLD signal does not coincide with the CLK in active low state, then the device exits in HOLD mode when the CLK reaches the next active low state. See Figure.2 for HOLD condition waveform. If /CS is driven active high during a HOLD condition, it resets the internal logic of the device. As long as /HOLD signal is low, the memory remains in the HOLD condition. To resume communication with the device, /HOLD must be driven active high, and /CS must be driven active low. See 12.11 for HOLD timing. |
类似零件编号 - FM25Q16 |
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类似说明 - FM25Q16 |
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