AD8362

Rev. D | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CHPF

DECL

INHI

PWDN

DECL

INLO

COMM

VREF

VTGT

VPOS

ACOM

COMM

CLPF

VSET

VOUT

ACOM

AD8362

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin

No.

Mnemonic

Description

Equivalent

Circuit

1, 8

COMM

Common Connection. Connect via low impedance to system common.

2

CHPF

Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.

3, 6

DECL

Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete

input circuit.

4, 5

INHI , INLO

Differential Signal Input Terminals. Input Impedance = 200 Ω. Can also be driven single-ended, in

which case, the input impedance reduces to 100 Ω.

Circuit A

7

PWDN

Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.

9

CLPF

Connection for Ground Referenced Loop Filter Integration (Averaging) Capacitor.

10, 16

ACOM

Analog Common Connection for Output Amplifier.

11

VSET

Setpoint Input. Connect directly to VOUT for measurement mode. Apply setpoint input to this pin for

controller mode.

Circuit B

12

VOUT

RMS Output. In measurement mode, VOUT is normally connected directly to VSET.

Circuit C

13

VPOS

Connect to 5 V Power Supply.

14

VTGT

The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower

target voltage increases the crest factor capacity. Normally connected to VREF.

Circuit D

15

VREF

General-Purpose Reference Voltage Output of 1.25 V. Usually connected only to VTGT.

Circuit E