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74AHC74PW 数据表(PDF) 10 Page - NXP Semiconductors |
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74AHC74PW 数据表(HTML) 10 Page - NXP Semiconductors |
10 / 18 page 74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 9 June 2008 10 of 18 NXP Semiconductors 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger 11. Waveforms Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays mna422 th tsu th tPHL tPHL tW tPLH tPLH tsu 1/fmax VM VM VM VM VI GND VI GND nCP input nD input VOH VOL nQ output VOH VOL nQ output |
类似零件编号 - 74AHC74PW |
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类似说明 - 74AHC74PW |
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