数据搜索系统,热门电子元器件搜索 |
|
EPCS16SI16N 数据表(PDF) 23 Page - Altera Corporation |
|
EPCS16SI16N 数据表(HTML) 23 Page - Altera Corporation |
23 / 38 page Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet 3–23 Serial Configuration Device Memory Access © December 2009 Altera Corporation Configuration Handbook (Complete Two-Volume Set) Read Device Identification Operation The read device identification operation code is b’1001 1111, with the MSB listed first. Only EPCS128 supports this operation. It reads the serial configuration device’s 8-bit device identification from the DATA output pin. If this operation is shifted in during an erase or write cycle, it is ignored and has no effect on the cycle that is in progress. Table 3–15 shows the serial configuration device identification. The device implements the read device identification operation by driving nCS low then shifting in the read device identification operation code followed by two dummy byte on ASDI. The serial configuration device’s 16-bit device identification is then shifted out on the DATA pin on the falling edge of DCLK, as shown in Figure 3–14. The device can terminate the read device identification operation by driving nCS high after reading the device identification at least once. Write Bytes Operation The write bytes operation code is b'0000 0010, with the MSB listed first. The write bytes operation allows bytes to be written to the memory. The write enable operation must be executed prior to the write bytes operation to set the write enable latch bit in the status register to 1. The write bytes operation is implemented by driving nCS low, followed by the write bytes operation code, three address bytes and a minimum one data byte on ASDI. If the eight least significant address bits (A[7..0]) are not all 0, all sent data that goes beyond the end of the current page is not written into the next page. Instead, this data is written at the start address of the same page (from the address whose eight LSBs are all 0). Drive nCS low during the entire write bytes operation sequence, as shown in Figure 3–15. If more than 256 data bytes are shifted into the serial configuration device with a write bytes operation, the previously latched data is discarded and the last 256 bytes are written to the page. However, if less than 256 data bytes are shifted into the serial configuration device, they are guaranteed to be written at the specified addresses and the other bytes of the same page are unaffected. Table 3–15. Serial Configuration Device Identification Serial Configuration Device Silicon ID (Binary Value) EPCS128 b'0001 1000 Figure 3–14. Read Device Identification Operation Timing Diagram (Note 1) Note to Figure 3–14: (1) Only EPCS128 supports read device identification operation. nCS DCLK ASDI DATA 0 1 2 3 4 5 6 7 8 9 10 20 21 23 24 25 26 27 28 29 30 31 32 Operation Code Two Dummy Bytes 15 14 13 321 0 765 43 210 MSB MSB High Impedance Silicon ID |
类似零件编号 - EPCS16SI16N |
|
类似说明 - EPCS16SI16N |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |