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EPCS4SI8N 数据表(PDF) 27 Page - Altera Corporation

部件名 EPCS4SI8N
功能描述  Serial Configuration Devices
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPCS4SI8N 数据表(HTML) 27 Page - Altera Corporation

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Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
3–27
Timing Information
© December 2009
Altera Corporation
Configuration Handbook (Complete Two-Volume Set)
Timing Information
Figure 3–18 shows the timing waveform for write operation to the serial configuration
device.
Table 3–16 defines the serial configuration device timing parameters for write
operation.
Figure 3–18. Write Operation Timing
nCS
DCLK
ASDI
DATA
tNCSH
tDSU
tNCSSU
tCH
tCL
tCSH
tDH
Bit n
Bit 0
Bit n
1
High Impedance
Table 3–16. Write Operation Parameters
Symbol
Parameter
Min
Typ
Max
Unit
fWCLK
Write clock frequency (from FPGA, download cable, or
embedded processor) for write enable, write disable,
read status, read silicon ID, write bytes, erase bulk, and
erase sector operations
——25
MHz
tCH
DCLK
high time
20
ns
tCL
DCLK
low time
20
ns
tNCSSU
Chip select (nCS) setup time
10
ns
tNCSH
Chip select (nCS) hold time
10
ns
tDSU
Data (ASDI) in setup time before rising edge on DCLK
5—
ns
tDH
Data (ASDI) hold time after rising edge on DCLK
5—
ns
tCSH
Chip select high time
100
ns
tWB (1)
Write bytes cycle time for EPCS1, EPCS4, EPCS16, and
EPCS64
—1.5
5
ms
Write bytes cycle time for EPCS128
2.5
7
ms
tWS (1)
Write status cycle time
5
15
ms
tEB (1)
Erase bulk cycle time for EPCS1
3
6
s
Erase bulk cycle time for EPCS4
5
10
s
Erase bulk cycle time for EPCS16
17
40
s
Erase bulk cycle time for EPCS64
68
160
s
Erase bulk cycle time for EPCS128
105
250
s
tES (1)
Erase sector cycle time for EPCS1, EPCS4, EPCS16,
and EPCS64
—2
3
s
Erase sector cycle time for EPCS128
2
6
s
Note to Table 3–16:
(1) These parameters are not shown in Figure 3–18.


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