数据搜索系统,热门电子元器件搜索 |
|
EPM9560 数据表(PDF) 35 Page - Altera Corporation |
|
EPM9560 数据表(HTML) 35 Page - Altera Corporation |
35 / 46 page Altera Corporation 35 MAX 9000 Programmable Logic Device Family Data Sheet Notes to tables: (1) These values are specified under the MAX 9000 device recommended operating conditions, shown in Table 15 on page 27. (2) See Application Note 77 (Understanding MAX 9000 Timing) for more information on test conditions for tPD1 and tPD2 delays. (3) This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This parameter applies for both global and array clocking as well as both macrocell and I/O cell registers. (4) Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB. (5) The tLPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode. (6) The tROW , tCOL, and tIOC delays are worst-case values for typical applications. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. Power Consumption The supply power (P) versus frequency (fMAX) for MAX 9000 devices can be calculated with the following equation: P = PINT + PIO = ICCINT × VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation: ICCINT = (A × MC TON) + [B × (MCDEV – MCTON)] + (C × MCUSED × f MAX × togLC) Table 24. Interconnect Delays Symbol Parameter Conditions Speed Grade Unit -10 -15 -20 MinMax MinMax MinMax t LOCAL LAB local array delay 0.5 0.5 0.5 ns t ROW FastTrack row delay (6) 0.9 1.4 2.0 ns t COL FastTrack column delay (6) 0.9 1.7 3.0 ns t DIN_D Dedicated input data delay 4.0 4.5 5.0 ns t DIN_CLK Dedicated input clock delay 2.7 3.5 4.0 ns t DIN_CLR Dedicated input clear delay 4.5 5.0 5.5 ns t DIN_IOC Dedicated input I/O register clock delay 2.5 3.5 4.5 ns t DIN_IO Dedicated input I/O register control delay 5.5 6.0 6.5 ns |
类似零件编号 - EPM9560 |
|
类似说明 - EPM9560 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |