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EPM9400 数据表(PDF) 25 Page - Altera Corporation

部件名 EPM9400
功能描述  Programmable Logic Device Family
Download  46 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM9400 数据表(HTML) 25 Page - Altera Corporation

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Altera Corporation
25
MAX 9000 Programmable Logic Device Family Data Sheet
Figure 11. MAX 9000 JTAG Waveforms
Table 13 shows the JTAG timing parameters and values for MAX 9000
devices.
f Fordetailedinformationon JTAGoperationinMAX 9000devices,referto
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices).
Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices
Symbol
Parameter
Min
Max
Unit
tJCP
TCK
clock period
100
ns
tJCH
TCK
clock high time
50
ns
tJCL
TCK
clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
25
ns
tJSZX
Update register high impedance to valid output
25
ns
tJSXZ
Update register valid output to high impedance
25
ns
TDO
TCK
tJPZX
tJPCO
tJPH
tJPXZ
tJCP
tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU
tJSH
tJSCO
tJSXZ


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