Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

3–25

Serial Configuration Device Memory Access

© December 2009

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

You must account for this delay before accessing the memory contents. Alternatively,

you can check the write in progress bit in the status register by executing the read

status operation while the self-timed erase cycle is in progress. The write in progress

bit is 1 during the self-timed erase cycle and 0 when it is complete. The write enable

latch bit in the status register is reset to 0 before the erase cycle is complete.

Erase Sector Operation

The erase sector operation code is b'1101 1000, with the MSB listed first. The erase

sector operation allows the user to erase a certain sector in the serial configuration

device by setting all bits inside the sector to 1 or 0xFF. This operation is useful for

users who access the unused sectors as general purpose memory in their applications.

The write enable operation must be executed prior to the erase sector operation so

that the write enable latch bit in the status register is set to 1.

The erase sector operation is implemented by first driving nCS low, then shifting in

the erase sector operation code and the three address bytes of the chosen sector on the

ASDI

pin. The three address bytes for the erase sector operation can be any address

inside the specified sector. (Refer to Table 3–3 through Table 3–7 for sector address

range information.) Drive nCS high after the eighth bit of the erase sector operation

code has been latched in. Figure 3–17 shows the timing diagram.

Immediately after the device drives nCS high, the self-timed erase sector cycle is

respective EPCS devices. You must account for this amount of delay before the

memory contents can be accessed. Alternatively, you can check the write in progress

bit in the status register by executing the read status operation while the erase cycle is

in progress. The write in progress bit is 1 during the self-timed erase cycle and 0 when

it is complete. The write enable latch bit in the status register resets to 0 before the

erase cycle is complete.

Figure 3–16. Erase Bulk Operation Timing Diagram

nCS

DCLK

ASDI

01234567

Operation Code

Figure 3–17. Erase Sector Operation Timing Diagram

Note to Figure 3–17:

(1) Address bit A[23] is a don't-care bit in EPCS64. Address bits A[23..21] are don't-care bits in EPCS16. Address bits A[23..19] are don't-

care bits in EPCS4. Address bits A[23..17] are don't-care bits in EPCS1.

nCS

DCLK

ASDI

01234567

89

28

29

30

31

Operation Code

24-Bit Address (1)

23

22

3

2

1

0

MSB