数据搜索系统,热门电子元器件搜索 |
|
ISL5314EVAL2 数据表(PDF) 2 Page - Intersil Corporation |
|
ISL5314EVAL2 数据表(HTML) 2 Page - Intersil Corporation |
2 / 17 page 2 FN4901.3 January 19, 2010 Pin Descriptions PIN NO. PIN NAME TYPE PIN DESCRIPTION 44-48, 1-3 C(7:0) Input 8-bit processor input data bus. C7 is the MSB. Data is written to the control register selected on A(3:0) on the rising edge of WR when WE is active. 42 WR Input Write clock for the processor interface. Parallel data is clocked into the chip on the rising edge of WR. 40 WE Input Write enable. Active low. WE must be active when writing data to the chip. 35-38 A(3:0) Input Processor interface address bus. These pins select the destination register for data on the C(7:0) bus. A3 is the MSB. 6 CLK Clock NCO and DAC clock. The phase accumulator and DAC output update on the rising edge of this clock. CLK can be asynchronous to the WR clock. 8 RESET Input Reset. Active low. Resets control registers to their default states (see register description table) and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur. 30 SCLK Input Serial clock. Polarity is programmable. See control word 12. May be asynchronous to CLK. If not used, connect to DGND. 27 SDATA Input Serial data. See control word 12. If not used, connect to DGND. 32 SSYNC Input Serial sync. See control word 12. If not used, connect to DGND. 9UPDATE Input Active low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0) pins. This pin is provided for updating an entire frequency word at once rather than byte by byte. 33, 34 PH(1:0) Input Phase offset bits. The phase of the output is shifted. If not used, these pins should be grounded. 00 – 0° reference 01 – 90° shift 10 – 180° shift 11 – 270° shift 4 ENOFR Input Enable offset frequency. Active high. When high, the offset frequency bus is enabled to the phase accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the contents of the offset frequency registers. If not used, the pin should be grounded. 10 COMPOUT Output Comparator output. 11 REFLO Input Connect to analog ground to enable the DAC’s internal 1.2V reference or connect to AVDD to disable the internal reference. 12 REFIO Input Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a 0.1µF cap to ground from the REFIO pin when a DC reference voltage is used. 13 FSADJ Full scale current adjust for the DAC. Use a resistor to ground (RSET) to adjust the full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET, where VFSADJ equals the reference voltage. 14 COMP1 Noise reduction for the DAC. Connect a 0.1µF cap to AVDD plane. 19 COMP2 Noise reduction for the DAC. Connect a 0.1µF cap to AGND plane. 18 IOUTA Output DAC current output. 17 IOUTB Output DAC complementary current output. 20 AVDD Power Analog supply voltage. 15, 16, 21, 24 AGND GND Analog ground. 7, 26, 31, 43 DVDD Power Digital supply voltage. 5, 25, 28, 29, 41 DGND GND Digital ground. 22, 23 IN+, IN- Input Comparator inputs. To power down the comparator, connect both of these pins to the analog power supply. This will conserve ~4mA of current. 39 NC NC No connect. ISL5314 |
类似零件编号 - ISL5314EVAL2 |
|
类似说明 - ISL5314EVAL2 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |