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ISL54102CQZ 数据表(PDF) 4 Page - Intersil Corporation |
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ISL54102CQZ 数据表(HTML) 4 Page - Intersil Corporation |
4 / 21 page 4 FN6275.5 June 4, 2008 DIGITAL OUTPUT CHARACTERISTICS VOH Output HIGH Voltage, IO = 8mA 2.4 V VOL Output LOW Voltage, IO = -8mA 0.4 V POWER SUPPLY REQUIREMENTS VD Supply Voltage 3 3.3 3.6 V ID Supply Current All available inputs driven by 165Mpixel/s TMDS signals. Default register settings ISL54100 387 435 mA ISL54101 357 405 mA ISL54102 370 415 mA ID Supply Current in Power-down Mode All available inputs driven by 165Mpixel/s TMDS signals. 20 26 mA AC TIMING CHARACTERISTICS (2-WIRE INTERFACE) fSCL SCL Clock Frequency 0 400 kHz tAA SCL LOW to SDA Data Out Valid 200 470 ns tBUF Time the Bus Must be Free Before a New Transmission Can Start 1.3 µs tLOW Clock LOW Time 1.3 0.1 µs tHIGH Clock HIGH Time 0.6 0.2 µs tSU:STA Start Condition Setup Time 0.6 0.03 µs tHD:STA Start Condition Hold Time 0.6 0.07 µs tSU:DAT Data In Setup Time 100 0.03 ns tHD:DAT Data In Hold Time 0 ns tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 160 ns NOTE: 2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 3. Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed. Electrical Specifications Specifications apply for VD = 3.3V, pixel rate = 165MHz, TA = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ, TMDS output load = 50 Ω, TMDS output termination voltage V TERM = 3.0V unless otherwise noted. SYMBOL PARAMETER COMMENT MIN (Note 2) TYP MAX (Note 2) UNIT tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA IN SDA OUT tF tLOW tBUF tAA tR FIGURE 1. 2-WIRE INTERFACE TIMING ISL54100, ISL54101, ISL54102 |
类似零件编号 - ISL54102CQZ |
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类似说明 - ISL54102CQZ |
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