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ISL59450 数据表(PDF) 5 Page - Intersil Corporation |
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ISL59450 数据表(HTML) 5 Page - Intersil Corporation |
5 / 37 page 5 FN7510.0 February 14, 2008 I2C Timing Diagram Serial Interface (I2C) Specifications SYMBOL PARAMETER CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT VOL SDA Output Buffer LOW Voltage IOL =4mA 0 0.4 V ILI Input Leakage Current on SCL VIN = 5.5V 0.1 1 µA ILO I/O Leakage Current on SDA VIN = 5.5V 0.1 1 µA TIMING CHARACTERISTICS fSCL SCL Frequency 400 kHz tLOW Clock LOW Time Measured at the 30% of VD crossing. 1.3 µs tHIGH Clock HIGH Time Measured at the 70% of VD crossing. 0 0.9 µs tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge. Both crossing 70% of VD. 0.6 µs tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VD to SCL falling edge crossing 70% of VD. 0.6 µs tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VD to SDA entering the 30% to 70% of VD window. 00.9 µs tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VD, to SDA rising edge crossing 30% of VD 0.6 µs tR SDA and SCL Rise Time From 30% to 70% of VD 20 + 0.1 x Cb ns tF SDA and SCL Fall Time From 70% to 30% of VD 20 + 0.1 x Cb ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 400 pF Cpin SDA and SCL Pin Capacitance 10 pF NOTE: 1. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT SCL SDA (INPUT TIMING) SDA (OUTPUT TIMING) tF tLOW tR ISL59450 |
类似零件编号 - ISL59450 |
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类似说明 - ISL59450 |
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